Staff Characterization Engineer

at Marvell Semiconductor in Boise, Idaho, United States

Job Description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact
The Marvell post silicon validation group designs and develops test platforms for validating multi-core Arm-based Network processors used in many communication infrastructure applications such as 5G base stations and cloud computing platforms. The electrical characterization team is a post silicon validation sub-group focused on the debug and characterization of SerDes and DDR interfaces on the processor. The SerDes interface use NRZ and PAM4 signaling for Ethernet, CPRI, JESD, and PCIe interfaces. DRAM interfaces include LPDDR5, DDR4/5 memory modules.
Characterization engineers are responsible for developing test platforms used and automated test suites to characterize the analog interfaces over process voltage and temperature (PVT) extremes to determine silicon viability for volume production.

What You Can Expect
As a member of our dynamic development team, you will be responsible for contributing to the analysis, and debug of high speed SerDes IO. In this role you will participate in debugging the SerDes analog interface to improve SerDes/PLL performance and resolve issues over PVT. Participation in these tasks will allow you to gain insight into the operation of state-of-the-art SerDes analog circuits including PLL's, Clock and Data Recovery circuits as well as Transmit FFE, Receiver CTLE and DFE equalization circuits.
In this role you will:

Contribute to debugging SerDes/PLL analog circuits for performance optimization or to root cause failures.
Electrical characterization/compliance testing of PCIe and Ethernet SerDes interfaces.
Contribute to the design of High-Speed PCB's used for electrical characterization/compliance testing.
Hardware support for the functional validation teams on lower speed IO including USB, EMMC & SPI.
Low-level protocol debug of PCIe and Ethernet interfaces including initialization and link training.

What We're Looking For

Bachelor's degree in Electrical Engineering or related fields and 3-5+ years of related professional experience Or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-4+ years of experience.

Prior experience with electrical characterization / compliance testing of PCIe, Ethernet, CPRI, JESD, or SerDes interfaces.
Python scripting experience.
JMP data analysis
High-Speed PCBDesign experience is a plus
Low-level protocol debug of PCIe and Ethernet interface experience is a plus

Expected Base Pay Range (USD)101,900 - 150,850, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit ElementsAt Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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Job Posting: 6508015

Posted On: May 20, 2024

Updated On: Jun 14, 2024

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