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Principal Engineer- Design

at Microchip Technology Inc. in Chandler, Arizona, United States

Job Description

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.   People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.   Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.   Visit our careers page to see what exciting opportunities and company perks await!   Job Description:   At Microchip NCS group, we are at the forefront of high-speed connectivity solutions, powering the next generation of automotive, industrial, and enterprise networks. Our team is dedicated to innovation, collaboration, and technical excellence. We are seeking a Senior Ethernet PHY Designer to join our world-class team and drive the development of cutting-edge multi-gig T1 PHY products. As a Senior Ethernet PHY Designer, you will play a key role in the architecture, design, and verification of high-performance multi-gigabit T1 Ethernet PHYs. You will collaborate with cross-functional teams to deliver robust, low-power, and high-speed solutions that meet stringent industry standards. This is an opportunity to shape the future of automotive and industrial Ethernet connectivity. The role will include working in the areas of RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design flow. Candidate will also be responsible for training and mentoring junior engineers to grow the team's capability. This positon require a proactive and motivated candidate with a proven record of success in a cross functional and cross site team environment.   Requirements/Qualifications:   Demonstrated experience in designing and delivering multi-gigabit PHYs, with a preference for T1 or automotive Ethernet applications Solid understanding of DSP elements, including DFE, FFE, echo cancellers, PGA, and related components Expertise in RTL coding using Verilog and SystemVerilog Proficient in chip-level design and integration activities, such as linting, CDC analysis, and power analysis Experience with IP and chip-level synthesis at 16nm and below Proficient in static timing analysis and achieving timing closure on complex SoCs Hands-on experience with the C programming language Proficiency in common UNIX scripting languages, including Perl, Python, and csh Strong debugging skills in both functional and gate-level simulations Familiarity with revision control tools such as CVS, Perforce, and DesignSync, including tagging and release methodologies Experience working with lab equipment, including oscilloscopes, logic analyzers, and VNAs Excellent analytical, problem-solving, and communication skills Experience with automotive and industrial Ethernet standards (e.g., 802.3bp, 802.3ch, 802.3cg) is highly desirable   Desired Skills: Experience with Verification Methodologies such as UVM/VMM Knowledge of Programming Languages such as C++ or System C Experience with Emulation/FPGA Prototyping for pre-silicon validation Knowledge and exposure to complete SOC RTL to GDS to silicon release flow is desired   Required Education: MS+ 7 years of experience or BS + 10 years of experience in Electrical/Electronic Engineering   Travel Time: 0% - 25%   Physical Attributes: Hearing, Seeing, Talking, Works Alone, Works Around Others   Physical Requirements: 80% sitting, 10% standing, 10% walking, 100% inside   Microchip Technology Inc is an equal opportunity/affirmative action... For full info follow application link.   Microchip is an Equal Opportunity/Affirmative Action Employer of Disabled/Veterans/Minorities/Women. We provide equal employment and affirmative action opportunities to applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability, or any other basis protected under applicable federal, state or local laws.    

 

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Job Posting: 7199534

Posted On: Sep 29, 2025

Updated On: Sep 29, 2025

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